The dimensions of semiconductor field effect transistors (FETs) have been steadily shrinking over the last thirty 30 years or so, as scaling to smaller dimensions leads to continuing device performance improvements. Planar FET devices have a conducting gate electrode positioned above a semiconducting channel, and electrically isolated from the channel by a thin layer of gate oxide. Current through the channel is controlled by applying voltage to the conducting gate.
For a given device length, the amount of current drive for an FET is defined by the device width (w). Current drive scales proportionally to device width, with wider devices carrying more current than narrower devices. Different parts of integrated circuits (ICs) require the FETs to drive different amounts of current, i.e., with different device widths, which is particularly easy to accommodate in planar FET devices by merely changing the device gate width (via lithography).
With conventional planar FET scaling reaching fundamental limits, the semiconductor industry is looking at more unconventional geometries that will facilitate continued device performance improvements. One such class of devices is a FinFET.
A FinFET is a double gate FET in which the channel is a semiconducting “Fin” of width w and height h, where typically w<h. The gate dielectric and gate are positioned around the fin such that current flows down the channel on the two sides of the Fin (generally, FinFETs do not use the fin top surface as part of the conducting channel).
FinFET devices typically include a fully depleted body in the Fin that provides several advantages over a conventional FET. These advantages include nearly ideal turn off in sub-threshold voltages, giving lower off-currents and/or allowing lower threshold voltages, no loss to drain currents from body effects, no ‘floating’ body effects (often associated with some silicon-on-insulator (SOI) FETs), higher current density, lower voltage operation, and reduced short channel degradation of threshold voltage and off current. Furthermore, FinFETs are more easily scaled to smaller physical dimensions and lower operating voltages than conventional and SOI FETs.
Bulk FinFET integration schemes have been introduced in the prior art, but these prior art methods require expensive source/drain isolation schemes such as recessed shallow trench isolation (STI). In view of the foregoing, there is a need for providing a simple isolation scheme for a structure including a FinFET which is low cost, yet provides good n-to-n, p-to-p and n-to-p isolation.